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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9708 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 8-bit, 100 msps+ txdac ? d/a converter functional block diagram +1.20v ref reflo ref io fs adj 50pf comp1 0.1mf current source array +5v avdd segmented switches latches digital data inputs (db7Cdb0) dvdd dcom clock sleep iouta ioutb comp2 acom 0.1m f +5v r set clock 0.1m f ad9708 features member of pin-compatible txdac product family 125 msps update rate 8-bit resolution linearity: 1/4 lsb dnl linearity: 1/4 lsb inl differential current outputs sinad @ 5 mhz output: 50 db power dissipation: 175 mw @ 5 v to 45 mw @ 3 v power-down mode: 20 mw @ 5 v on-chip 1.20 v reference single +5 v or +3 v supply operation packages: 28-lead soic and 28-lead tssop edge-triggered latches fast settling: 35 ns full-scale settling to 0.1% applications communications signal reconstruction instrumentation product description the ad9708 is the 8-bit resolution member of the txdac series of high performance, low power cmos digital-to-analog converters (dacs). the txdac family, which consists of pin compatible 8-, 10-, 12-, and 14-bit dacs, was specifically opti- mized for the transmit signal path of communication systems. all of the devices share the same interface options, small outline package and pinout, thus providing an upward or downward component selection path based on performance, resolution and cost. the ad9708 offers exceptional ac and dc performance while supporting update rates up to 125 msps. the ad9708s flexible single-supply operating range of +2.7 v to +5.5 v and low power dissipation are well suited for portable and low po wer applications. its power dissipation can be further reduced to 45 mw, without a significant degradation in performance, by lowering the full-scale current output. in addi- tion, a power-d own mode reduces the standby power dissipa- tion to approximately 20 mw. the ad9708 is manufactured on an advanced cmos process. a segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. edge-triggered input latches and a temperature compensated bandgap reference have been inte- grated to provide a com plete monolithic dac solution. flexible supply options support +3 v and +5 v cmos logic families. the ad9708 is a current-output dac with a nominal full-scale output current of 20 ma and > 100 k w output impedance. txdac is a registered trademark of analog devices, inc. differential current outputs are provided to support single- ended or differential applications. the current outputs may be directly tied to an output resistor to provide two complemen- tary, single-ended voltage outputs. the output voltage compliance range is 1.25 v. the ad9708 contains a 1.2 v on-chip reference and reference control amplifier, which allows the full-scale output current to be simply set by a single resistor. the ad9708 can be driven by a variety of external reference voltages. the ad9708s full-scale current can be adjusted over a 2 ma to 20 ma range without any degradation in dynamic performance. thus, the ad9708 may operate at reduced power levels or be adjusted over a 20 db range to provide additional gain ranging capabilities. the ad9708 is available in 28-lead soic and 28-lead tssop packages. it is specified for operation over the industrial tem- perature range. product highlights 1. the ad9708 is a member of the txdac product family, which provides an upward or downward component selection path based on resolution (8 to 14 bits), performance and cost. 2. manufactured on a cmos process, the ad9708 uses a pro- prietary switching technique that enhances dynamic perfor- mance well beyond 8- and 10-bit video dacs. 3. on-chip, edge-triggered input cmos latches readily interface to +3 v and +5 v cmos logic families. the ad9708 can support update rates up to 125 msps. 4. a flexible single-supply operating range of +2.7 v to +5.5 v and a wide full-scale current adjustment span of 2 ma to 20 ma allows the ad9708 to operate at reduced power levels (i.e., 45 mw) without any degradation in dynamic performance. 5. a temperature compensated, 1.20 v bandgap reference is included on-chip providing a complete dac solution. an external reference may be used. 6. the current output(s) of the ad9708 can easily be config- ured for various single-ended or differential applications.
dc specifications parameter min typ max units resolution 8 bits monotonicity guaranteed over specified temperature range dc accuracy 1 integral linearity error (inl) e1/2 1/4 +1/2 lsb differential nonlinearity (dnl) e1/2 1/4 +1/2 lsb analog output offset error e0.025 +0.025 % of fsr gain error (without internal reference) e10 2 +10 % of fsr gain error (with internal reference) e10 1 +10 % of fsr full-scale output current 2 2.0 20.0 ma output compliance range e1.0 1.25 v output resistance 100 k w output capacitance 5 pf reference output reference voltage 1.08 1.20 1.32 v reference output current 3 100 na reference input input compliance range 0.1 1.25 v reference input resistance 1 m w small signal bandwidth (w/o c comp1 ) 4 1.4 mhz temperature coefficients offset drift 0 ppm of fsr/ c gain drift (without internal reference) 50 ppm of fsr/ c gain drift (with internal reference) 100 ppm of fsr/ c reference voltage drift 50 ppm/ c power supply supply voltages avdd 5 2.7 5.0 5.5 v dvdd 2.7 5.0 5.5 v analog supply current (i avdd )2530ma digital supply current (i dvdd ) 6 36ma supply current sleep mode (i avdd ) 8.5 ma power dissipation 6 (5 v, i outfs = 20 ma) 140 175 mw power dissipation 7 (5 v, i outfs = 20 ma) 190 mw power dissipation 7 (3 v, i outfs = 2 ma) 45 mw power supply rejection ratio?avdd e0.4 +0.4 % of fsr/v power supply rejection ratio?dvdd e0.025 +0.025 % of fsr/v operating range e40 +85 c notes 1 measured at iouta, driving a virtual ground. 2 nominal full-scale current, i outfs , is 32 the i ref current. 3 use an external buffer amplifier to drive any external load. 4 reference bandwidth is a function of external cap at comp1 pin. 5 for operation below 3 v, it is recommended that the output current be reduced to 12 ma or less to maintain optimum performance. 6 measured at f clock = 50 msps and f out = 1.0 mhz. 7 measured as unbuffered voltage output into 50 w r load at iouta and ioutb, f clock = 100 msps and f out = 40 mhz. specifications subject to change without notice. (t min to t max , avdd = +5 v, dvdd = +5 v, i outfs = 20 ma, unless otherwise noted) e2e rev. b ad9708especifications
dynamic specifications p arameter min typ max units dynamic performance maximum output update rate (f clock ) 100 125 msps output settling time (t st ) (to 0.1%) 1 35 ns output propagation delay (t pd )1ns glitch impulse 5 pv-s output rise time (10% to 90%) 1 2.5 ns output fall time (10% to 90%) 1 2.5 ns output noise (i outfs = 20 ma) 50 pa/ ? hz output noise (i outfs = 2 ma) 30 pa/ ? hz ac linearity to nyquist signal-to-noise and distortion ratio f clock = 10 msps; f out = 1.00 mhz 50 db f clock = 50 msps; f out = 1.00 mhz 50 db f clock = 50 msps; f out = 12.51 mhz 48 db f clock = 100 msps; f out = 5.01 mhz 50 db f clock = 100 msps; f out = 25.01 mhz 45 db total harmonic distortion f clock = 10 msps; f out = 1.00 mhz e67 dbc f clock = 50 msps; f out = 1.00 mhz e67 e62 dbc f clock = 50 msps; f out = 12.51 mhz e59 dbc f clock = 100 msps; f out = 5.01 mhz e64 dbc f clock = 100 msps; f out = 25.01 mhz e48 dbc spurious-free dynamic range to nyquist f clock = 10 msps; f out = 1.00 mhz 68 dbc f clock = 50 msps; f out = 1.00 mhz 62 68 dbc f clock = 50 msps; f out = 12.51 mhz 63 dbc f clock = 100 msps; f out = 5.01 mhz 67 dbc f clock = 100 msps; f out = 25.01 mhz 50 dbc notes 1 measured single ended into 50 w load. specifications subject to change without notice. digital specifications p arameter min typ max units digital inputs logic 1 voltage @ dvdd = +5 v 3.5 5 v logic 1 voltage @ dvdd = +3 v 2.1 3 v logic 0 voltage @ dvdd = +5 v 0 1.3 v logic 0 voltage @ dvdd = +3 v 0 0.9 v logic 1 current e10 +10 m a logic 0 current e10 +10 m a input capacitance 5pf input setup time (t s )2.0ns input hold time (t h )1.5ns latch pulsewidth (t lpw ) 3.5 ns specifications subject to change without notice. 0.1% 0.1% t s t h t lpw t pd t st db0edb7 clock iouta or ioutb figure 1. timing diagram (t min to t max , avdd = +5 v, dvdd = +5 v, i outfs = 20 ma, single-ended output, iouta, 50 v doubly terminated, unless otherwise noted) ad9708 e3e rev. b (t min to t max , avdd = +5 v, dvdd = +5 v, i outfs = 20 ma unless otherwise noted)
ad9708 e4e rev. b absolute maximum ratings* with parameter respect to min max units avdd acom e0.3 +6.5 v dvdd dcom e0.3 +6.5 v acom dcom e0.3 +0.3 v avdd dvdd e6.5 +6.5 v clock, sleep dcom e0.3 dvdd + 0.3 v digital inputs dcom e0.3 dvdd + 0.3 v iouta, ioutb acom e1.0 avdd + 0.3 v comp1, comp2 acom e0.3 avdd + 0.3 v refio, fsadj acom e0.3 avdd + 0.3 v reflo acom e0.3 +0.3 v junction temperature +150 c storage temperature e65 +150 c lead temperature (10 sec) +300 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may effect device reliability. thermal characteristics thermal resistance 28-lead 300 mil soic q ja = 71.4 c/w q jc = 23 c/w 28-lead tssop q ja = 97.9 c/w q jc = 14.0 c/w pin configuration 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) 28 27 26 25 24 23 22 21 ad9708 nc = no connect (msb) db7 db6 db5 db4 db3 db2 db1 db0 nc nc nc nc nc nc clock dvdd dcom nc avdd comp2 iouta ioutb acom comp1 fs adj refio reflo sleep caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9708 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. pin function descriptions pin no. name description 1 db7 most significant data bit (msb). 2e7 db6edb1 data bits 1e6. 8 db0 least significant data bit (lsb). 9e14, 25 nc no internal connection. 15 sleep power-down control input. active high. contains active pull-down circuit, thus may be left unterminated if not used. 16 reflo r eference ground when internal 1.2 v refer ence used. connect to avdd to disable internal reference. 17 refio reference input/output. serves as reference input when internal reference disabled (i.e., tie reflo to avdd). serves as 1.2 v reference output when internal reference activated (i.e., tie reflo to acom). requires 0.1 m f capacitor to acom when internal reference activated. 18 fs adj full-scale current output adjust. 19 comp1 bandwidth/noise reduction node. add 0.1 m f to avdd for optimum performance. 20 acom analog common. 21 ioutb complementary dac current output. full-sc ale current when all data bits are 0s. 22 iouta dac current output. full-scale current when all data bits are 1s. 23 comp2 internal bias node for switch driver circuitry. decouple to acom with 0.1 m f capacitor. 24 avdd analog supply voltage (+2.7 v to +5.5 v). 26 dcom digital common. 27 dvdd digital supply voltage (+2.7 v to +5.5 v). 28 clock clock input. data latched on positive edge of clock. ordering guide temperature package package model range descriptions options* ad9708ar e40 c to +85 c 28-lead 300 mil soic r-28 ad9708aru e40 c to +85 c 28-lead tssop ru-28 ad9708-eb evaluation board *r = small outline ic; ru = thin small outline ic. warning! esd sensitive device
ad9708 e5e rev. b definitions of specifications linearity error (also called integral nonlinearity or inl) linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. differential nonlinearity (or dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. monotonicity a d/a converter is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of zero is called offset error. for iouta, 0 ma output is expected when the inputs are all 0s. for ioutb, 0 ma output is expected when all inputs are set to 1s. gain error the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. output compliance range the range of allowable voltage at the output of a current-output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown resulting in nonlinear performance. temperature drift temperature drift is specified as the maximum change from the ambient (+25 c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full-scale range (fsr) per degree c. for reference drift, the drift is reported in ppm per degree c. power supply rejection the maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. settling time the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. glitch impulse asymmetrical switching times in a dac give rise to undesired output transients that are quantified by a glitch impulse. it is specified as the net area of the glitch in pv-s. spurious-free dynamic range the difference, in db, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. signal-to-noise and distortion (s/n+d, sinad) ratio s/n+d is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/n+d is expressed in decibels. total harmonic distortion thd is the ratio of the rms sum of the first six harmonic components to the rms value of the measured output signal. it is expressed as a percentage or in decibels (db). dvdd dcom retimed clock output* digital data tektronix awg-2021 lecroy 9210 pulse generator clock output 50 v 20pf 50 v 20pf to hp3589a spectrum/ network analyzer 50 v input * awg2021 clock retimed such that digital data transitions on falling edge of 50% duty cycle clock. +1.20v ref reflo ref io fs adj 50pf comp1 0.1 m f current source array +5v avdd segmented switches latches dvdd dcom clock sleep iouta ioutb comp2 acom 0.1 m f +5v r set 2k v 0.1 m f ad9708 50 v figure 2. basic ac characterization test setup
ad9708 e6e rev. b typical ac characterization curves frequency e mhz sinad/thd e db 70 60 40 0.1 1 100 10 50 65 55 45 thd @ 10msps thd @ 50msps thd @ 100msps sinad @ 10msps sinad @ 100msps sinad @ 50msps figure 3. sinad/thd vs. f out (avdd and dvdd = 5.0 v) frequency e mhz sinad/thd e db 70 60 40 0.1 1 100 10 50 65 55 45 thd @ 10msps thd @ 50msps thd @ 100msps sinad @ 10msps sinad @ 100msps sinad @ 50msps figure 6. sinad/thd vs. f out (avdd and dvdd = 3.0 v) f clock = 25msps f out = 7.81mhz sfdr = +60.7dbc amplitude = 0dbfs 0 e100 start: 0hz stop: 12.5mhz 10db e div figure 9. single-tone spectral plot @ 25 msps frequency e mhz sinad/thd e db 70 60 40 0.1 1 100 10 50 65 55 45 thd @ 10msps thd @ 50msps thd @ 100msps sinad @ 10msps sinad @ 100msps sinad @ 50msps figure 4. sinad/thd vs. f out (differ- ential output, avdd and dvdd = 5.0 v) frequency e mhz sinad/thd e db 70 60 40 0.1 1 100 10 50 65 55 45 thd @ 10msps thd @ 50msps thd @ 100msps sinad @ 10msps sinad @ 100msps sinad @ 50msps figure 7. sinad/thd vs. f out (differ- ential output, avdd and dvdd = 3.0 v) f clock = 125msps f out = 27.0mhz sfdr = +52.7dbc amplitude = 0dbc 0 start: 0hz stop: 62.5mhz e100 10db e div figure 10. single-tone spectral plot @ 125 msps frequency e mhz sinad e db 55 50 30 1 100 10 40 45 35 i outfs = 20ma i outfs = 10ma i outfs = 5ma i outfs = 2.5ma figure 5. sinad vs. i outfs @ 100 msps frequency e mhz sinad e db 52 50 42 0.1 10 1 46 48 44 i outfs = 20ma i outfs = 5ma i outfs = 2.5ma i outfs = 10ma figure 8. s inad vs. i outfs @ 20 msps time e 5ns/div volts 0.5 0.4 0.3 0.2 0.1 0.0 e0.1 0.6 e0.2 figure 11. step response (avdd = +5 v or +3 v, dvdd = +5 v or +3 v, 50 v doubly terminated load, single-ended output, i outa , i outfs = 20 ma, t a = +25 8 c, unless otherwise noted)
ad9708 e7e rev. b functional description figure 12 shows a simplified block diagram of the ad9708. the ad9708 consists of a large pmos current source array capable of providing up to 20 ma of total current. the array is divided into 31 equal currents that make up the five most significant bits (msbs). the remaining 3 lsbs are also implemented with equally weig hted current sources whose sum total equals 7/8th of an msb current source. implementing the upper and lower bits with current sources helps maintain the dac?s high output impedance (i.e. > 100 k w ). all of these current sources are switched to one or the other of the two output nodes (i.e., iouta or ioutb) via pmos differential current switches. the switches are b ased on a new architecture that drastically improves distortion performance. the analog and digital sections of the ad9708 have separate power supply inputs (i.e., avdd and dvdd) that can operate independently over a 2.7 volt to 5.5 volt range. the digital section, which is capable of operating up to a 125 msps clock rate, consists of edge-triggered latches and segment decoding logic circuitry. the analog section includes the pmos current sources, the associated differential switches, a 1.20 v bandgap voltage reference and a reference control amplifier. the full-scale output current is regulated by the reference con- trol amplifier and can be set from 2 ma to 20 ma via an exter- nal resistor, r set . the external resistor, in combination with both the reference control amplifier and voltage reference v refio , sets the reference current i ref , which is mirrored over to the segmented current sources with the proper scaling factor. the full-scale current, i outfs , is thirty-two times the value of i ref . dac transfer function the ad9708 provides complementary current outputs, iouta and ioutb. iouta will provide a near full-scale current output, i outfs , when all bits are high (i.e., dac code = 255), while ioutb, the complementary output, provides no current. the current output appearing at iouta and ioutb are a function of both the input code and i outfs and can be expressed as: i outa = ( dac code /256) i outfs (1) i outb = (255 C dac code )/256 i outfs (2) where dac code = 0 to 255 (i.e., decimal representation). as previously mentioned, i outfs is a function of the reference current i ref , which is nominally set by a reference voltage v refio and external resistor r set . it can be expressed as: i outfs = 32 i ref (3) where i ref = v refio / r set (4) the two current outputs will typically drive a resistive load directly. if dc coupling is required, iouta and ioutb should be directly connected to matching resistive loads, r load , which are tied to analog common, acom. note, r load may repre- sent the equivalent load resistance seen by iouta or ioutb as would be the case in a doubly terminated 50 w or 75 w cable. the single-ended voltage output appearing at the iouta and ioutb nodes is simply: v outa = i outa r load (5) v outb = i outb r load (6) note the full-scale value of v outa and v outb should not exceed the specified output compliance range to maintain specified distortion and linearity performance. the differential voltage, v diff , appearing across iouta and ioutb is: v diff = ( i outa C i outb ) r load (7) substituting the values of i outa , i outb , and i ref ; v diff can be expressed as: v diff = {(2 dac code C 255)/256}/ (32 r load / r set ) v refio (8) voltage reference and control amplifier the ad9708 contains an internal 1.20 v bandgap reference that can be easily disabled and overridden by an external refer- ence. refio serves as either an input or output depending on whether the internal or an external reference is selected. if reflo is tied to acom, as shown in figure 13, the internal reference is activated and refio provides a 1.20 v output. in this case, the internal reference must be compensated externally with a ceramic chip capacitor of 0.1 m f or greater from refio to reflo. note that refio is not designed to drive any ex- ternal load. it should be buffered with an external amplifier having an input bias current less than 100 na if any additional loading is required. +1.20v ref reflo refio fs adj 50pf comp1 0.1 m f current source array +5v avdd segmented switches latches dvdd dcom clock sleep iouta ioutb comp2 acom 0.1 m f +5v r set 2k v 0.1 m f ad9708 i outb v outb r load 50 v v outa r load 50 v i outa v diff = v outa C v outb clock i ref v refio digital data inputs (db7Cdb0) figure 12. functional block diagram
ad9708 e8e rev. b 50pf comp1 +1.2v ref avdd reflo current source array 0.1 m f +5v refio fs adj 2k v 0.1 m f ad9708 additional load optional external ref buffer figure 13. internal reference configuration the internal reference can be disabled by connecting reflo to avdd. in this case, an external reference may then be applied to refio as shown in figure 14. the external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. note that the 0.1 m f compensation capacitor is not required since the internal reference is disabled, and the high input impedance (i.e., 1 m w ) of refio minimizes any loading of the external reference. 50pf comp1 +1.2v ref avdd reflo current source array 0.1 m f avdd refio fs adj r set ad9708 external ref i ref = v refio /r set avdd reference control amplifier v refio figure 14. external reference configuration the ad9708 also contains an internal control amplifier that is used to regulate the dac?s full-scale output current, i outfs . the control amplifier is configured as a v-i converter, as shown in figure 14, such that its current output, i ref , is determined by the ratio of the v refio and an external resistor, r set , as stated in equation 4. the control amplifier allows a wide (10:1) adjustment span of i outfs over a 2 ma to 20 ma range by setting i ref between 62.5 m a and 625 m a. the wide adjustment span of i outfs provides several applic ation benefits. the f irst benefit relates directly to the power dissipation of the ad 9708, which is proportional to i outfs (refer to the power dissipation section). the second benefit relates to the 20 db adjustment, which is useful for system gain control purposes. the small signal bandwidth of the reference control amplifier is approximately 1.8 mhz and can be reduced by connecting an external capacitor between comp1 and avdd. the output of the control amplifier, comp1, is internally compensated via a 50 pf capacitor that limits the control amplifier small-signal bandwidth and reduces its output impedance. any additional external capacitance further limits the bandwidth and acts as a filter to reduce the noise contribution from the reference amplifier. if i ref is fixed for an application, a 0.1 m f ceramic chip capacitor is recommended. i ref can be varied for a fixed r set by disabling the internal refer ence and varying the common-mode voltage over its compliance range of 1.25 v to 0.10 v. refio can be driven by a single-supply amplifier or dac, thus allowing i ref to be var- ied for a fixed r set . since the input impedance of refio is approximately 1 m w , a simple r-2r ladder dac configured in the voltage mode topology may be used to control the gain. this circuit is shown in figure 15 using the ad7524 and an external 1.2 v reference, the ad1580. note another ad9708 could also be used as the gain control dac since it can also provide a programmable unipolar output up to 1.2 v. analog outputs and output configurations the ad9708 produces two complementary current outputs, i outa and i outb , which may be converted into complementary singl e-ended voltage outputs, v outa and v outb , via a load resistor, r load , as described in the dac transfer f unction section. figure 16 shows the ad9708 configured to provide a positive unipolar output range of approximately 0 v to +0.5 v for a double terminated 50 w cable for a nominal full-scale current, i outfs , of 20 ma. in this case, r load represents the equivalent load resistance seen by iouta or ioutb and is equal to 25 w . the unused output (iouta or ioutb) can be connected to acom directly or via a matching r load . different values of i outfs and r load can be selected as long as the posi- tive compliance range is adhered to. ad9708 iouta ioutb 21 50 v 25 v 50 v v outa = 0 to +0.5v i outfs = 20ma 22 figure 16. 0 v to +0.5 v unbuffered voltage output alternatively, an amplifier could be configured as an i-v converter thus converting iouta or ioutb into a negative unipolar 1.2v 50pf comp1 +1.2v ref avdd reflo current source array avdd refio fs adj r set ad9708 i ref = v ref /r set avdd optional bandlimiting capacitor v ref v dd r fb out1 out2 agnd db7edb0 ad7524 ad1580 0.1v to 1.2v figure 15. single-supply gain control circuit
ad9708 e9e rev. b voltage. figure 17 shows a buffered singled-ended output con- figuration in which the op amp, u1, performs an i-v conversion on the ad9708 output current. u1 provides a negative unipolar output voltage and its full-scale output voltage is simply the product of r fb and i outfs . the full-scale output should be set within u1?s voltage output swing capabilities by scaling i outfs and/or r fb . an improvement in ac distortion performance may result with a reduced i outfs , since the signal current u1 will be required to sink and will be subsequently reduced. note, the ac distortion performance of this circuit at higher dac update rates may be limited by u1?s slewing capabilities. ad9708 22 iouta ioutb 21 c opt 200 v u1 v out = i outfs 3 r fb i outfs = 10ma r fb 200 v figure 17. unipolar buffered voltage output iouta and ioutb also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. the positive output compliance range is slightly dependent on the full-scale output current, i outfs . it degrades slightly from its nominal 1.25 v for an i outfs = 20 ma to 1.00 v for an i outfs = 2 ma. applications requiring the ad9708?s output (i.e., v outa and/or v outb ) to extend up to its output compliance range should size r load accordingly. operation beyond this compliance range will adversely affect the ad9708?s linea rity. the differential voltage, v diff , existing between v outa and v outb may also be converted to a single-ended voltage via a transformer or differential amplifier configuration. refer to the differential output configuration section for more information. digital inputs the ad9708?s digital input consists of eight data input pins and a clock input pin. the 8-bit parallel data inputs follow standard positive binary coding where db7 is the most significant bit (msb) and db0 is the least significant bit (lsb). the digital interface is implemented using an edge-triggered master slave latch. the dac output is updated following the rising edge of the clock as shown in figure 1 and is designed to support a clock rate as high as 125 msps. the clock can be operated at any duty cycle that meets the specified latch pulsewidth. the setup-and-hold times can also be varied within the clock cycle as long as the specified minimum times are met; although the location of these transition edges may affect digital feedthrough and distortion performance. the digital inputs are cmos compatible with logic thresholds, v threshold set to approximately half the digital positive supply (dvdd) or v threshold = dvdd /2 ( 20%) figure 18 shows the equivalent digital input circuit for the data and clock inputs. the sleep mode input is similar, except that it contains an active pull-down circuit, thus ensuring that the ad9708 remains enabled if this input is left disconnected. the internal digital circuitry of the ad9708 is cap able of operating over a digital supply range of 2.7 v to 5.5 v. as a result, the digital inputs can also accommodate ttl levels when dvdd is set to accommodate the maximum high level voltage, v oh(max) , of the ttl drivers. a dvdd of 3 v to 3.3 v w ill typically ensure upper compatibility of most ttl logic famil ies. dvdd digital input figure 18. equivalent digital input since the ad9708 is capable of being updated up to 125 msps, the quality of the clock and data input signals are important in achieving the optimum performance. the drivers of the digital data interface circuitry should be specified to meet the minimum setup-and-hold times of the ad9708 as well as its required min/ max input logic level thresholds. typically, the selection of the slowest logic family that satisfies the above conditions will result in the lowest data feedthrough and noise. digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch. the insertion of a low value resistor network (i.e., 20 w to 100 w ) between the ad9708 digital inputs and driver outputs may be helpful in reducing any overshooting and ringing at the digital inputs that contribute to data feedthrough. for longer run lengths and high data update rates, strip line techniques with proper termination resistors should be considered to maintain clean digital inpu ts. also, operating the ad9708 with reduced logic swings and a corre- sponding digital supply (dvdd) will also reduce data feedthrough. the external clock driver circuitry should provide the ad9708 with a low jitter clock input meeting the min/max logic levels while providing fast edges. fast clock edges will help minimize any jitter that will manifest itself as phase noise on a recon- structed waveform. however, the clock input could also be driven by via a sine wave, which is centered around the digital threshold (i.e., dvdd/2), and meets the min/max logic threshold. this may result in a slight degradation in the phase noise, which becomes more noticeable at higher sampling rates and output frequencies. note, at higher sampling rates the 20% tolerance of the digital logic threshold should be considered since it will affect the effective clock duty cycle and subsequently cut into the required data setup-and-hold times. sleep mode operation the ad9708 has a power-down function that turns off the output current and reduces the supply current to less than 8.5 ma over the specified supply range of 2.7 v to 5.5 v and tempera- ture range. this mode can be activated by applying a logic level 1 to the sleep pin. this digital input also contains an active pull-down circuit that ensures the ad9708 remains enabled if this input is left disconnected. the sleep input with active pull-down requires <40 m a of drive current. the power-up and power-down characteristics of the ad9708 are dependent on the value of the compensation capacitor con- nected to comp2 (pin 23). with a nominal value of 0.1 m f, the ad9708 takes less than 5 m s to power down and approximately 3.25 ms to power back up.
ad9708 e10e rev. b power dissipation the power dissipation, p d , of the ad9708 is dependent on several factors, including: (1) avdd and dvdd, the power supply voltages; (2) i outfs , the full-scale current output; (3) f clock , the update rate; (4) and the reconstructed digital input waveform. the power dissipation is directly proportional to the analog supply current, i avdd , and the digital supply current, i dvdd. i avdd is directly proportional to i outfs , as shown in figure 19, and is insensitive to f clock . conversely, i dvdd is dependent on both the digital input wave- form, f clock , and digital supply dvdd. figures 20 and 21 show i dvdd as a function of full-scale sine wave output ratios (f out /f clock ) for various update rates with dvdd = 5 v and dvdd = 3 v, respectively. note, how i dvdd is reduced by more than a factor of 2 when dvdd is reduced from 5 v to 3 v. applying the ad9708 power and grounding considerations in systems seeking to simultaneously achieve high speed and high performance, the implementation and construction of the printed circuit board design is often as important as the circuit design. proper rf techniques must be used in device selection placement and routing and supply bypassing and grounding. the evaluation board for the ad9708, which uses a four layer pc board, serves as a good example for the above mentioned considerations. the evaluation board provides an illustration of the recommended printed circuit board ground, power and signal plane layouts. proper grounding and decoupling should be a primary objective in any high speed system. the ad9708 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. in general, avdd, the analog supply, should be decoupled to acom, the analog common, as close to the chip as physically possible. simi- larly, dvdd, the digital supply, should be decoupled to dcom as close as physically as possible. for those applications requiring a single +5 v or +3 v supply for both the analog and digital supply, a clean analog supply may be generated using the circuit shown in figure 22. the circuit consists of a differential lc filter with separate power supply and return lines. lower noise can be attained using low esr type electrolytic and tantalum capacitors. i outfs e ma 30 0 220 46 81012141618 25 20 15 10 5 i avdd e ma figure 19. i avdd vs. i outfs ratio (f out /f clk ) 18 16 0 0.01 1 0.1 i dvdd e ma 8 6 4 2 12 10 14 5msps 25msps 50msps 100msps 125msps figure 20. i dvdd vs. ratio @ dvdd = 5 v 100 m f elect. 10-22 m f tant. 0.1 m f cer. ttl/cmos logic circuits +5v or +3v power supply ferrite beads avdd acom figure 22. differential lc filter for single +5 v or +3 v applications maintaining low noise on power supplies and ground is critical to obtaining optimum results from the ad9708. if properly implemented, ground planes can perform a host of functions on high speed circuit boards: bypassing, shielding, current trans- port, etc. in mixed signal design, the analog and digital portions of the board should be distinct from each other, with the analog ground plane confined to the areas covering the analog signal traces, and the digital ground plane confined to areas covering the digital interconnects. all analog ground pins of the dac, reference and other analog components, should be tied directly to the analog ground plane. the two ground planes should be connected by a path 1/8 to 1/4 inch wide underneath or within 1/2 inch of the dac to maintain optimum performance. care should be taken to ensure that the ground plane is uninterrupted over crucial signal paths. on the digital side, this includes the digital input lines running to the dac as well as any clock signals. on the analog side, this includes the dac output signal, reference signal and the supply feeders. the use of wide runs or planes in the routing of power lines is also recommended. this serves the dual role of providing a low series impedance power supply to the part, as well as providing some free capacitive decoupling to the appropriate ground plane. it is essential that care be taken in the layout of signal and power ground interconnects to avoid inducing extraneous voltage drops in the signal ground paths. it is recommended that all connections be short, direct and as physically close to the package as possible in order to minimize the sharing of conduc- tion paths between different currents. when runs exceed an inch in length, strip line techniques with proper termination resistor ratio (f out /f clk ) 8 0 0.01 1 0.1 i dvdd e ma 6 4 2 5msps 25msps 50msps 100msps 125msps figure 21. i dvdd vs. ratio @ dvdd = 3 v
ad9708 e11e rev. b should be considered. the necessity and value of this resistor will be dependent upon the logic family used. for a more detailed discussion of the implementation and construction of high speed, mixed signal printed circuit boards, refer to analog devices? application notes an-280 and an-333. differential output configurations for applications requiring the optimum dynamic performance and/or a bipolar output swing, a differential output configura- tion is suggested. a differential output configuration may con- sists of either an rf transformer or a differential op amp configuration. the transformer configuration is well suited for ac coupling applications. it provides the optimum high fre- quency performance due to its excellent rejection of common- mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. it also provides electrical isolation and the ability to deliver twice the power to the load (i.e., assuming no source termination). the differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain, and/or level shifting. figure 23 shows the ad9708 in a typical transformer coupled output configuration. the center-tap on the primary side of the tran sformer must be connected to acom to provide the necessary dc current path for both iouta and ioutb. the complemen- tary voltages appearing at iouta and ioutb (i.e., v outa and v outb ) swing symmetrically around acom and should be maintained within the specified output compliance range of the ad9708. a differential resistor, r diff , may be inserted in applications in which the output of the transformer is connected to the load, r load , via a passive reconstruction filter or cable. r diff is determined by the transformer?s impedance ratio and provides the proper source termination. note that approxi- mately half the signal power will be dissipated across r diff . r load ad9708 22 21 mini-circuits t1-1t optional r diff iouta ioutb figure 23. differential output using a transformer an op amp can also be used to perform a differential to single- ended conversion as shown in figure 24. the ad9708 is configured with two equal load resistors, r load , of 25 w . the differential voltage developed across iouta and ioutb is converted to a single-ended signal via the differential op amp configuration. an optional capacitor can be installed across iouta and ioutb forming a real pole in a low-pass filter. the addition of this capacitor also enhances the op amps distortion performance by preventing the dacs high slewing output from overloading the op amp?s input. ad9708 22 iouta ioutb 21 c opt 500 v 225 v 225 v 500 v 25 v 25 v ad8072 figure 24. dc differential coupling using an op amp the common-mode rejection of this configuration is typically determined by the resistor matching. in this circuit, the differ- ential op amp circuit is configured to provide some additional signal gain. the op amp must operate off a dual supply since its output is approximately 1.0 v. a high speed amplifier capable of preserving the differential performance of the ad9708 while meeting other system level objectives (i.e., cost, power) should be selected. the op amps differential gain, its gain setting resis- tor values and full-scale output swing capabilities should all be considered when optimizing this circuit. the differential circuit shown in figure 25 provides the neces- sary level-shifting required in a single supply system. in this case, avdd, which is the positive analog supply for both the ad9708 and the op amp, is also used to level-shift the differ- ential output of the ad9762 to midsupply (i.e., avdd/2). ad9708 22 iouta ioutb 21 c opt 500 v 225 v 225 v 1k v 25 v 25 v ad8072 1k v avdd figure 25. single-supply dc differential coupled circuit ad9708 evaluation board general description the ad9708-eb is an evaluation board for the ad9708 8-bit d/a converter. careful attention to layout and circuit design, combined with a prototyping area, allows the user to easily and effectively evaluate the ad9708 in any application where high resolution, high speed conversion is required. this board allows the user the flexibility to operate the ad9708 in various configurations. possible output configurations include transformer coupled, resistor terminated, inverting/noninverting and differential amplifier outputs. the digital inputs are designed to be driven directly from various word generators, with the on-board option to add a resistor network for proper load termination. provisions are also made to operate the ad9708 with either the internal or external reference, or to exercise the power-down feature. refer to the application note an-420 using the ad9760/ ad9762/ad9764-eb evaluation board for a thorough description and operating instructions for the ad9708 evalua- tion board.
ad9708 e12e rev. b 1098765432 1 r4 10 9 8 7 6 5 4 3 2 1 r7 dvdd 10 9 8 7 6 5 4 3 2 1 r3 1098765432 1 dvdd r6 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 p1 10 9 8 7 6 5 4 3 2 1 r5 dvdd 10 9 8 7 6 5 4 3 2 1 r1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 c19 c1 c2 c25 c26 c27 c28 c29 16 pindip res pk 16 15 14 13 12 11 10 1 2 3 4 5 6 7 c30 c31 c32 c33 c34 c35 c36 16 pindip res pk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 clock dvdd dcom nc avdd comp2 i outa i outb acom comp1 fs adj refio reflo sleep u1 ad9708 avdd ct1 a 1 a r15 49.9 v clk jp1 ab 3 2 1 j1 tp1 extclk c7 1 m f c8 0.1 m f avdd a c9 0.1 m f tp8 2 avdd tp11 c11 0.1 m f tp10 tp9 r16 2k v tp14 jp4 c10 0.1 m f out 1 out 2 tp13 r17 49.9 v pdin j2 a a a avdd 3 jp2 tp12 tp7 a c6 10 m f avcc b6 tp6 a c5 10 m f avee b5 tp19 a agnd b4 tp18 tp5 c4 10 m f tp4 avdd b3 tp2 dgnd b2 c3 10 m f tp3 dvdd b1 r20 49.9 v j3 c12 22pf a a r14 0 a 4 5 6 1 3 t1 j7 r38 49.9 v j4 a a jp6a jp6b a r13 open c13 22pf c20 0 r12 open a b a jp7b b a jp7a r10 1k v b a jp8 r9 1k v a b a r35 1k v jp9 r18 1k v a 3 7 6 2 4 ad8047 c21 0.1 m f a c22 1 m f r36 1k v c23 0.1 m f a c24 1 m f avee avcc r37 49.9 v j6 a 3 7 6 2 4 1 2 3 jp5 c15 0.1 m f a avee r46 1k v c17 0.1 m f a 1 2 3 jp3 a b avcc a cw r43 5k v r45 1k v c14 1 m f a r44 50 v extrefin j5 a r42 1k v c16 1 m f a avcc c18 0.1 m f u7 6 2 4 a vin vout gnd ref43 98765432 1 r2 10 a 1098765432 1 dvdd r8 u6 a ad8047 out2 out1 u4 figure 26. evaluation board schematic
ad9708 e13e rev. b figure 27. silkscreen layer?top figure 28. component side pcb layout (layer 1)
ad9708 e14e rev. b figure 30. power plane pcb layout (layer 3) figure 29. ground plane pcb layout (layer 2)
ad9708 e15e rev. b figure 31. solder side pcb layout (layer 4) figure 32. silkscreen layer?bottom
e16e c2979be1e4/99 printed in u.s.a. outline dimensions dimensions shown in inches and (mm). 28-lead, 300 mil soic (r-28) 0.0125 (0.32) 0.0091 (0.23) 8 8 0 8 0.0291 (0.74) 0.0098 (0.25) 3 45 8 0.0500 (1.27) 0.0157 (0.40) 28 15 14 1 0.7125 (18.10) 0.6969 (17.70) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 28-lead tssop (ru-28) 28 15 14 1 0.386 (9.80) 0.378 (9.60) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8? 0? ad9708 rev. b

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